The present invention relates to logic division techniques for logically assigning the electronic circuits of an ASIC (application specific integrated circuit) or a logic device to programmable chips. More particularly, the invention relates to a logic division apparatus, such as a computer system or computer implemented device, and method or process which takes into consideration design efficiency and operation timing when assigning the electronic circuits of a large-scale ASIC or a logic device to a plurality of programmable chips.
For example, when the electronic circuits of a large ASIC or a logic device are to be implemented in a programmable chip allocation process, the logic scale or the number of available I/O pins of each chip sometimes makes it difficult to accommodate all logic information in a single programmable chip. In such a case, it is necessary to divide the logic information about the electronic circuits constituting the ASIC or logic device into a plurality of groups for assignment to a plurality of programmable chips.
The programmable chips for use with this invention are those fabricated under the so-called FPGA (field programmable gate-array) formula. In its basic structure, this type of programmable chip has programmable logic modules regularly laid out with wiring regions interposed therebetween. The chips are semi-custom ICs that may be programmed by the user into a logic device comprising from 2,000 to 20,000 gates.